1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory comprising a bit line and a word line.
2. Description of the Background Art
A memory (ferroelectric memory) provided with memory cells including ferroelectric capacitors on intersectional positions between bit lines and word lines arranged to intersect with each other is know in general. This memory performs a rewrite operation after performing a read operation, when reading data of the memory cells.
FIG. 9 is a voltage waveform diagram for illustrating operations of a ferroelectric memory of related art. Bit lines (H) in FIG. 9 is bit lines to which a reading voltage corresponding to data “H” is outputted, while bit lines (L) in FIG. 9 is bit lines to which a reading voltage corresponding to data “L” is outputted. The ferroelectric memory of related art performs read and rewrite operations in periods T101 to T103 (one cycle), with reference to FIG. 9.
More specifically, the period T101 is a period for a read operation. In this period T101, the potential of a selected word line is set to Vcc, while the potential of nonselected word lines is set to 0 V. The ferroelectric memory brings the bit lines (H) and the bit lines (L) into floating states. Thus, data “H” is read to the bit lines (H), while data “L” is read to the bit line L. Data “L” is written in both memory cells corresponding to the bit lines (H) and the bit lines (L) by the read operation. The period T102 is a period for a first rewrite operation. In this period T102, the potential of the selected word line is set to Vcc, while the potential of the nonselected word lines is set to ⅓ Vcc. The potential of the bit lines (H) is set to 0V, while the potential of the bit lines (L) is set to ⅔ Vcc. Thus, data “L” is rewritten in the memory cells corresponding to the bit lines (H), while no data is written in the memory cells corresponding to the bit lines (L). The period T103 is a period for a second rewrite operation. In this period T103, the potential of the selected word line is set to 0 V, while the potential of the nonselected word lines is set to ⅔ Vcc. The potential of the bit lines (H) is set to VCC, while the potential of the bit lines (L) is set to ⅓ Vcc. Thus, data “H” is written in the memory cells corresponding to the bit lines (H), while no data is written in the memory cells corresponding to the bit lines (L).
In the ferroelectric memory of related art, the respective potentials of the bit lines and the word lines are controlled in the aforementioned manner, whereby data is read in the period T101 while data is rewritten in the periods T102 and T103.
In the ferroelectric memory of related art, however, a period during which a voltage (0V) other than the voltages responsive to the read operation and the first rewrite operation are applied to the selected word line and the bit lines (L) is provided between the period T101 (read operation) and the period T102 (first rewrite operation) as shown in FIG. 9. A period during which a voltage (0V) other than the voltages responsive to the first rewrite operation and the second rewrite operation are applied to the nonselected word lines and the bit lines (L) is provided between the period T102 (first rewrite operation) and the period T103 (second rewrite operation). Thus, a period of time necessary for one cycle including a read operation, a first rewrite operation and a second rewrite operation is disadvantageously increased. Consequently, it is disadvantageously difficult to operate the ferroelectric memory at a high speed.